EVALUATION OF SOLDERABLE FINISHES FOR SURFACE MOUNT AND FINE PITCH ASSEMBLY

FOR

SHIPLEY EUROPE LIMITED

Produced By:

Bob Willis
Electronic Presentation Services
2 Fourth Avenue
Chelmsford 
Essex CM1 4HA
England.

Tel:  (44) 01245 351502
Fax: (44) 01245 496123
Email: eps@bobwillis.co.uk
Home Page: http://www.bobwillis.co.uk

This copy of the report is not the final copy as that is now out of print. The report does not include any photographs or result sheets but may be useful to engineers looking at evaluating different solderable finishes. For further information of the choice of different coating contact either the author or Shipley Europe.

CONTENTS

1.		Introduction

2.		Evaluation Procedure

3.		Solderable Finishes Evaluated

4.		Industry Solderable Finishes

5.		Assembly Procedure

6.		Artificial Ageing Tests

7.		Solderability Measurements

8.		Soldering and Assembly Yield Graphs

			Printing Yields

			Placement Yields

			Reflow Yields

			Wave Solder Yields

9.		Microsection Examinations

10.	Conclusions

1.	Introduction

	The test programme was designed to evaluate the assembly yields which may be achieved with different protective coatings and solderable finishes on printed boards. At present there exists considerable debate on the benefits of flat surfaces on the screen printing of solder paste, placement of chip and fine pitch components without much specific data. The test programme provides information on the advantages and disadvantages of different finishes to assist engineering, sales and marketing departments. 

	The test programme was also designed to examine the effects on solderability of multiple heating processes commonly used in modern electronic assembly. The programme also demonstrates how coatings can stand up to exposure to high temperatures during multiple processing and develop a test procedure to evaluate individual coatings. The benefits of nitrogen soldering were not included in this initial evaluation.

2.	Evaluation Procedure

	The test board used for the evaluation contained both chip and fine pitch component footprints and was designed for automatic assembly. To minimise the cost and delay, test board designs already available and used by major pick and place manufacturers were used for all trials. This also minimised the time involved in programming the assembly of such boards and the sourcing of components. It was, however, necessary to arrange for a stencil to be produced for the printing of solder paste on one of the board. 

	Although it is preferable that testing be run at a manufacturing site to gain the benefit of an independent view, it would be very difficult to organise this type of exercise in an OEM. All assembly operations on the test boards were conducted at Dynapert, Colchester. However,  Marconi Communications, Chelmsford was involved in the inspection of the boards after assembly and soldering operations.

	The assembly processes used are outlined in diagrams 1 & 2 with the relevant visual inspection points and, where sample pads would be tested for solderability, are shown in the assembly procedure. All visual inspection was based on the draft European standards IEC 1191-1 which are aligned with the existing MIL/IPC standards.

	The test conditions for the assembly processes of adhesive cure, solder paste reflow and wave soldering were generally based on the requirement of the test board and the proposed European specification CECC 00802 for surface mount processes for component quality.

	A second test board is being processed to examine assembly yields only on fine pitch components < 0.025" pitch and 0402 miniature chip components. This second board will be assembled and soldered using solder paste and reflow technology only. The assembly is being conducted by Panasonic but the results are not yet available.

3.	Solderable Finishes Evaluated

	The following solderable finishes were included in this evaluation.  A group of boards was processed within two weeks of their initial manufacture. All solderability testing and artificial ageing was conducted within three weeks of the boards manufacture.

	The boards were produced from FR4 fibre glass with total of 1oz copper finish prior to the different coating application. The solder resist was a photo imagable mask selected to provide compatibility with the solderable finishes application.

		Solder Levelled Tin/Lead (HASL)

		OSP Organic Solderable Protection (A)	

		Immersion Tin

		Immersion Tin/Lead

		Nickel/Gold

		OSP Organic Solderable Protection (B)

4.	Industry Solderable Finishes

	The following is a brief review of the solderable and protective finishes which are available and being used in the industry. The finishes are currently used for printed boards which will contain both conventional and surface mount components.  

	TIN/LEAD REFLOW

	Tin/lead has been the standard finish in the UK industry for many years due to its use as an etch resist for the production of plated through hole boards when subtractive processes have been adopted. It has provided an ideal production solution to protecting the copper surfaces during the final copper etching process. It has also proved useful as it provides a solderable finish for the protection of the copper pads and tracking for subsequent soldering operations.

	With the increase in modern manufacturing methods using wave soldering and reflow soldering the finish has proved unacceptable due to the circuit's exposure to high temperatures during assembly, which causes reflow of the tin/lead coating under any solder resist coatings. This has led to lifting and de-lamination of the resist.  

	It has also been necessary for the tin/lead plate to be reflowed during PCB manufacture prior to solder resist coating. The reason for reflowing the tin/lead has been undertaken for two reasons:

		During the etching stage tin/lead slivers are left due to the undercutting which takes place during etching.  If not removed the slivers are trapped under the solder resist coating and during the assembly process shorts between tracking.

		The second reason or benefit for reflowing the tin/lead plate has been the improvement in long term solderability of the circuit. The tin/lead plate has a short solderability life, but if reflowed the surface is no longer porous and provides a longer shelf life. A minimum of one year's shelf life should be obtained from a surface coating of five microns after it has been reflowed.

	Unfortunately all tin/lead coatings which are reflowed or are applied to the circuit in a liquid form will tend to form a convex meniscus of solder on the circuitry. This is generally of no consequence to conventional assembly processes but can lead to poor yields during surface mount assembly.

	BRUSHED TIN/LEAD PLATE

	The brushed tin/lead process has been offered over the last few years by PCB manufacturers as a compromise for surface mount assembly as it provides a flat surface for component mounting and for screen printing. It probably became popular as it was a simple solution to the reflow process which resulted in uneven pad geometry for component placement. A further benefit was that printed board manufacturers could avoid the investment in solder levelling equipment and still offer a "Surface Mount Finish".

	The process has the disadvantages that the tin/lead remains in a plated state and can become unsolderable within six months, it also still has the problems of tin/lead slivers. This is probably how the finish got its name of brushed tin/lead as all surfaces were mechanically brushed to remove any tin/lead slivers from the surface of the board prior to solder resist coating. 

	SOLDER LEVELLED

	The solder levelling process became popular in the mid 80's due to the quality improvements which could be obtained. Eliminating the solder coating under the resist reduced the possibility of the resist lifting during the assembly soldering operation. It provided a guaranteed solderable surface from the PCB manufacture. A tin/lead thickness of >5um will provide a solderable finish for in excess of one year. It also provides a further benefit to the assembler of stressing the board. If the solder resist coating was poor or the lamination of a multilayer circuit was questionable, then it would generally show up during exposure to the molten solder bath prior to shipment to the customer.

	The solder levelling process also eliminated significant mismatch between circuitry and the resist apertures. This was due to only limited temperature being applied to the laminate prior to resist application. With the tin/lead reflow process the laminate is exposed to soldering temperatures which exceed the laminate's glass transition temperature. This causes expansion and contraction due to the stress in the laminate which is no longer held by the copper foil.

	
GOLD OVER NICKEL

	Gold is a traditional finish used in the electronics industry due to excellent electrical finish, corrosion resistance and, when required, good solderability. 

	There has been some resistance to the use of gold due to concerns of reliability of the final solder fillet. In the past gold has been widely used for connectors; it was also used in the 1970's for a solderable coating on boards. In both cases the ill-informed use of thick > 1um gold coating lead to the formation of gold/tin intermetalics which in turn lead to weak and fragile solder joints.

	Ever since, soldering to gold has been avoided particularly in high reliability applications like military and aerospace. Many existing standards relating to assembly and soldering require all gold coatings to be removed prior to the final soldering operations. 

	Over the last three years thin gold on copper and thin gold <0.25um over nickel have become popular finishes for surface mount boards. They have provided an ideal assembly surface, highly solderable and an aid to inspection due to the contrasting colour between component leads and the solder paste.

	FLUX LACQUER

	The protection of the copper pads during storage and assembly prior to soldering are of prime importance However, the cost of the printed circuit is also an important issue particularly in consumer electronics. Surface mount technology is being used in all sectors of the electronics industry; inevitably it is being used in the consumer industry.

	The use of flux lacquer as a protective coating applied to a copper pad is particularly widely used in the high volume TV/VCR industry dominated by the Japanese and Korean companies. Its use is generally confined to single sided boards.

	The flux lacquer materials are supplied by a wide range of suppliers, particularly those companies who existingly supply soldering fluxes to the PCB industry.

	The coating is generally applied by dip, spray or roller coating. Unfortunately all coating methods provide an inconsistent coating to the board surface, with the spray coating method probably being the most popular. 

	The coating provides a limited life expectancy due to the porosity of the coating and to its inconsistent coating thickness The material is now being used by selected companies as part of a two part process. The lacquer is used as a secondary coating after the copper surface has been chemically treated and protected by a proprietary treatment. Limitations of the coating have been its short shelf life, inconsistent coating thickness and incompatibility with Low Residue/No Clean fluxes.

	A further problem has been seen when using the coating on boards which are to be flux soldered. In the case of flow soldering the components are held in place on the underside of the board with adhesive. In cases where the coating is thick the bond between the adhesive and the component is with the lacquer coating and not the printed board. During the fluxing and soldering operation the bond strength between the adhesive and lacquer can drop, causing components to be lost during contact with the solder bath.

	It is common for the soldering process to be blamed for this loss of adhesion, but only limited force is applied to components during wave contact. For example, measurements of as little as 10-20 grams have been recorded acting on SOIC's during contact with the wave.

	The use of flux lacquers is undoubtedly a cheap option for providing a limited shelf life protection to the bare board. It does, however, suffer from the same problems as the protective coatings like Entek. Multiple high temperature exposures affects the solderability of the remaining pads, thus causing soldering problems.   

	OSP - PROTECTIVE COATINGS

	The protective coatings are generally defined as organic coatings. The most common coatings are benzotriazole and imidazole; both are organic nitrogen compounds. Benzotriazole has long been recognised as an anti-tarnish coating used in the general metal finishing industry. Inhibitor coatings are extremely thin and essentially invisible on the copper surface.

	The coatings protect the copper by chemically bonding to the surface and prevent the reaction between the copper and oxygen. The coating may be applied by dip or spray coating and followed by a rinse operation to remove any residues remaining on the solder mask surface. If required, the coating may be removed and re-applied to rejuvenate a surface which has become solderable. 

	If required, the surfaces would need to be re-cleaned with an acid etch and rinse prior to re-treatment.

	The protective coatings have been used for many years by large volume manufacturers for surface mount products, an example of which is IBM. The limitations of the coating is its general inability to stand up to multiple soldering operations. The coatings are degraded by exposure to high temperature and become unsolderable with mildly activated soldering fluxes. The use of high activity water soluble fluxes have often been used on second side wave soldering processes requiring thorough cleaning.

	The coatings are also susceptible to damage by high humidity storage which can degrade the solderability. Incorrect handling by assembly staff has also been seen to affect the coating due to the introduction of handling soils.      

	NEW TECHNOLOGY FINISHES

	There are a number of new processes being introduced into the industry specifically designed for SMT. The three new process finishes still use tin/lead coatings but it is their method of application which has caused them to be considered new techniques.

Note: A video tape on solderable coatings and their introduction to companies is available from EPS or the SMART Group.

		SIPAD

		SIPAD developed by Siemens is used on the finished board after solder mask coating. The solder mask coating must be relatively thick as it is required to define the position and height of the solder coating. The process requires solder paste to be stencil printed into the solder mask openings and onto the copper pads. As cleaning is easy on an unassembled board, activated pastes may be used without difficulty. After the solder paste is reflowed the domed molten meniscus is then flattened using a hot metal plate. As the metal plate cools to below the melting point of the solder a flat surface is achieved with the solder filling the solder mask opening.  

		OPTIPAD

		In the OPTIPAD process a temporary solder mask is used to create a mould around the land areas on the circuit board with the molten solder forced under pressure into the apertures. A membrane then seals the board surface during the solder solidification. After removal from the process equipment the temporary solder mask is stripped. The result is a well defined solder deposit of a controlled height and surface flatness.

		OPTIPAD is a registered trademark of SMW Elecktronik, Germany

		PPT  (Precision Pad Technology)

		The PPT process is a variation on the previous two processes. As in the SIPAD process, solder paste is used to provide the tin/lead coating. A dry film resist is used to create a mould around the individual pads on the circuit board. The solder paste is applied by stencil printing and reflowed in a standard reflow oven.

		In the case of PPT a fixture is used to help control the position of the solder paste and to create a dimple effect on the surface of the pad surface. By using different fixtures the surface topography of the pad may be changed to aid coverage and adhesion of the sticky flux which is required for component positioning and to aid soldering.

		PPT (Precision Pad Technology) is a registered trade mark of Mask Technology  

		SOLDERPOSIT

		Solderposit is an immersion non-electrolytic solder plating bath process specially developed for coating printed board surfaces with a near eutectic solderable tin/lead coating. The coating may then be fused to provide a surface which is solderable and a surface which aids solder paste printing and component placement due to its flat topography.

		A more traditional tin/lead coating overcomes the concerns of many engineers over the long term storage reliability of protective coatings and the possible solder joint reliability problems of gold coatings. Solderposit, being a tin/lead coating, does not provide the ease of inspection given by gold and copper surfaces. The alternative colour, when compared with the tin/lead solder paste and the plated component terminations, provides an ideal indicator to unsoldered joints after manufacture.
		
		SOLDERPOSIT is a registered trade mark of the Shipley Company Inc

           
5.	Assembly Procedure

	The assembly of the boards was conducted as illustrated in the flow diagrams (fig 1 and 2) using equipment at Dynapert, Colchester. Solder paste printing was conducted using a stencil made from 0.006" brass with a nickel coating. The placement and glue dispensing was conducted using Dynapert equipment. The 0.050" and 0.025" parts were assembled on to the board also using a Dynapert system.

	Reflow soldering and glue curing was conducted using a Surf Systems inline oven IR 400. The temperature profiles used for both glue curing and reflow were established to be the worst case time and temperature as indicated by IEC specifications CECC 00 802 for component compatibility testing. Using this criteria it indicates the likely success or failure of a coating in modern production.

	Sample components were tested for satisfactory curing prior to wave soldering. Sample board were also held for measurement of the thickness of the solder paste deposit, results may be include in any final editorial. 

	MIXED TECHNOLOGY BOARDS

SOLDERABILITY TEST ON SAMPLE PADS

ADHESIVE APPLICATION 

COMPONENT PLACEMENT

PLACEMENT INSPECTION

ADHESIVE CURE

SOLDERABILITY TEST 

WAVE SOLDER

SOLDER JOINT INSPECTION

Figure 1.

	SINGLE SIDE REFLOW

SOLDERABILITY TEST ON SAMPLE PADS

SOLDER PASTE PRINTING

COMPONENT PLACEMENT

PLACEMENT INSPECTION

REFLOW SOLDER

SOLDER JOINT INSPECTION

SOLDERABILITY TEST ON SAMPLE PADS

	DOUBLE SIDED REFLOW

SOLDERABILITY TEST ON SAMPLE PADS

SOLDER PASTE APPLICATION

COMPONENT PLACEMENT

PLACEMENT INSPECTION

REFLOW SOLDER

SOLDERABILITY TEST ON SAMPLE PADS

Figure 2.

6.	Artificial Ageing Tests

	There are two common ageing tests used in the industry one is steam ageing and the other is dry ageing. Both are designed to accelerate surface and interface ageing. The artificial ageing was used as a reference for the life expectancy of the coating and for comparison with the results obtained from the solderability test on the assembly samples. All solderability tests on artificially aged samples were performed on the same size pads.

	STEAM AGEING 

	The samples from each board were subjected to steam ageing using the test method outlined in BS6221, IEC 326-2 Printed Wiring Boards Part 2 Methods of Test. Each sample is exposed to 60 min in a steam chamber after first purging the chamber with nitrogen and obtaining the correct stable environment. After exposure the samples are removed and the solderability test procedure is followed. 

	DRY AGEING

	During dry ageing the test samples were subjected to elevated temperature of 155oC at a steady state for 16  hours to examine surface oxide formation and the decrease of solderability at the substrate interface. The procedure for dry ageing is outlined in BS2011 and IEC 68-2-3.

	Each of the samples were then tested with wetting measurements taken from five pads per sample using the wetting balance equipment. The resulting force curves are included in this report.  

	REFERENCE BOARDS

SOLDERABILITY TEST ON SAMPLE PADS

ARTIFICIAL AGEING OF REFERENCE BOARDS

SOLDERABILITY TEST ON SAMPLE PADS

Figure 10.

7.	Solderability Measurements

	The existing rotary dip solderability test method used by the printed board industry is very limited. It is difficult to demonstrate the subtle changes which take place on boards as they are subjected to multiple heating operations during the manufacture of the boards or during assembly. To provide repeatable results  the wetting balance was used to assess the changes in solderability on pads on each of the test boards. The same dimension pad was tested on each of the samples to aid comparison of the result between different finishes.

	At present there is no standard for testing solderability of surface mount pads; there are, however, proposals being discussed. Solderability measurements were conducted using the Multicore Must 2 wetting balance incorporating a micro globule to test the pads. The system was used as it allows automatic traverse of sample pads which is very important for multiple tests. Two methods were investigated prior to conducting the final test programme, this allowed the most repeatable procedure to be used. The following procedures were conducted on sample copper pads measuring 0.050" x 0.040" finished with a nickel/gold finish.

	1.	A sample was removed from a circuit board featuring a series of five pads and finished so that the edge of each of the pads extended to the edge of the board. The  board sample was placed in a modified holder to allow the board sample to be lowered at an angle of 45o to the solder pellet. The tests were conducted at 235oC using a 25mg solder globule on a 2mm globule block with an immersion depth of 0.1mm. The immersion speed for the tests were 1mm/s with a dwell time of 5 seconds.

		The 25mg globule was used for each pad to be tested without contacting the adjacent pad. Due to the size of the pad under test a new pellet was applied to the block after each test. It was also necessary to remove the occasional solder spike from the pads to avoid them touching the globule block and affecting the next test result. The tests were conducted using both pure rosin and activated rosin flux to assist repeatability of assessment.

	2.	Samples were tested using the above technique but with the sample board mounted at 90o allowing the solderable finish to be fully in contact with the solder globule. The test sample was more difficult to align and to remove the solder spikes after test. The second series of tests were performed using pure rosin flux. 

	The results show that the first method of test with the pads presented at 45o to the solder globule provided the most repeatable results and were used for the rest of the programme. During the final test programme the test pads were reduced in size 0.040" x 0.040" these were used for all other testing. A total of five measurements were taken for each of the samples under test.

There are a number proposed methods of evaluating the plots produced from the wetting balance equipment. The first and most accepted method is that the wetting force achieved on a particular sample must be a minimum of two thirds of the maximum achievable wetting force obtainable on a similar device or sample. The maximum wetting force is normally achieved by testing a sample using an activated flux to obtain the best possible wetting force curve.  This criteria is covered in specifications produced by IPC, IEC and BSI.     

8.	Soldering And Assembly Yield Graphs

	The graphs show the yield results from the Dynapert test board. The results are shown in total PPM defects for the groups of boards processed. Although the total defect level is high the difference between board finishes can be seen. The level of defects would be lower on a stable process and board design.

	During screen printing of solder paste the main defects found were scooping or skipped joints this is were solder paste is either not present or only partially present around the outer edge of the pad. This is a common defect where the surface coating thickness on the pads varies.

	The component placement defects were mainly misplaced parts which were not centrally placed on the pad surface or over hanging the termination point by more than 25% of the terminal width. Both screen printing and placement was also affected by the flatness of the board surface. The solder levelled boards exhibited the least flat board surfaces.

	The defects associated with the reflow soldering operations were either solder shorts on fine pitch or poor wetting of the pad surfaces after second side reflow. The poor wetting was only seen on immersion tin and the organic coatings.

	After wave soldering the faults found were short circuits and skipped joints as with the reflowed boards the shorts were seen on all boards. Most of the shorts were due to the design of the board. The skipped joints seen mainly on SOT23 devices particularly on boards exposed to the reflow, adhesive cure and wave soldering operations.      

	The board used for this part of the test programme featured 0.025" pitch parts for the reflow samples and 0805 and mini SOTs on the wave solder samples. A list of the parts used and the number of solderable lands is listed below.

	The second test board features pitches below 0.025" with 0402 passive parts assembled by reflow soldering. Due to delays in using the Panasonic demonstration facility the results are not included in this report.

	
	Dynapert Test Board

	8	SOIC14		Small Outline Integrated Circuit
	4	PLCC84		Plastic Leaded Chip Carrier
	2	QFP100		Quad Flat Pack
	112	1206 Resistors	Resistor 0.120" x 0.060"
	112	0805 Resistors	Resistor 0.080" x 0.050"
	60	SOT23		Small Outline Transistor
	84	SOT23 (Mini)	Small Outline Transistor
	48	MELF Diodes	Metal Electrode Face Bonded

	The total number of components on the board for reflow soldering was 430 giving a total of 1720 terminations used for soldering trials. The trial boards which were wave soldered contained less components, the PLCC and QFP's were left off the boards for this part of the trial.

9.	Microsection Examination

	Microsection were taken from the assembled boards after processing which showed that all solder joints produced were of a satisfactory standard. No voiding was evident on any of the sample boards examined in this evaluation. In the case of the gold boards the solder joints formed to the underlying material were satisfactory with no evidence of gold rich interfaces.

10.	Conclusions

	The following are the conclusions which can be drawn from the results obtained during this exercise.

		The solderable finish which is specified for surface mount boards can have an effect on the screen printing of solder paste, placement of all surface mount components and the subsequent solder joint quality and process yield results.

		The quality in terms of parts per million could be improved on the test board used for this exercise provided a more stable process could have been developed prior to starting the test programme. The difference in assembly yields caused by board finish selection would still be observed even with a stable process.

		The solder paste printing quality was satisfactory for all finishes apart from the solder levelled board where evidence of solder scoop and skips were seen due to the dome of the pad entering the stencil opening.

		The minor placement problems were again mainly attributable to the uneven finish on the pad surfaces. 

		Variations in solderability were generally seen on all finishes due to artificial ageing and the number of soldering operations. Dry ageing has long been considered to be the most effective ageing process as opposed to steam ageing. Attributing the correct time and temperature to dry ageing to simulate a year's real life storage is still a problem to the industry.

		When selecting a coating for any new product a engineer should consider the number of soldering operations the board is going to be subjected to due to the effect on solderability. Consideration should also be given to the printed board fabrication stages and the effect of high temperature process on the flatness of the board and thire effect on assembly operations.

		A further consideration during selection of the coating is the compatability of current and future assembly processes like conductive adhesives, wire bonding, direct die attachment and low resistance pressure contact.