PIC 16F18344 PORTA.5 issue


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  1. #1
    Junior Member davroski's Avatar
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    Default PIC 16F18344 PORTA.5 issue

    Hi,
    Basically, I'm struggling to get PORTA.5 to do anything

    I have PORTA.5 linked to PORTA.4, with 5 as output and 4 as logic input.

    A5 is PPS'd to be a comparator output linking to A4 as input to another process.

    ANSELA and TRISA are set accordingly. (as are comparator and PPS settings)

    Nothing appears on the A4/A5 link.
    If I reverse A4/A5 (using A4 as output and A5 as input) the expected levels appear, but A4 doesn't seem to be readable.

    It's like as if A5 is tristated off. As far as I can see from the datasheet there's nothing special about A5.

    Trying the simplest of things like toggling the pins with a timer in a loop works fine with A4 as the output but not when A5 is the output.

    Suspecting the chip, I eventually (it's a 20 pin SOIC) decided to replace it and found the new IC gave the same results.

    I've done some dumb things before, like trying to make MCLR into an output (!), and it'll probably be my fault yet again, but for the life of me I can't see the solution.

    Thanks

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    Senior Member Stephen Moss's Avatar
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    Default Re: PIC 16F18344 PORTA.5 issue

    Double check your ANSELA setting to ensure PORTA.5 is set to Digital I/O. If it is it sounds like it may be open collector, try using a pull up resistor to 5V (say 4K7 or 5K1) and see it if works then.
    If the pull-up resistor solves the problem then if you have not already done so try adding ADCONA.5 = 0 after your other settings for that pin to ensure the pin is on Push-Pull mode rather than open collector. Although Push-Pull mode apears to be the POR default it may be that the something is setting it to open drain in the background.

    Personally, I like to always perform register writes to configure the things I am using as I want them, even if the data sheet states they are they way at POR for two reasons...
    1) I can see in my code how the device is configured (do not have to refer back to the data sheet to see if I made an omission or did not set it due to the POR state being what I wanted)
    2) If the POR state in the datasheet is correct it does not hurt to have it there (belt & braces) but if the stated was POR is wrong I know the device is correctly configured for my application.

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  • #3
    Junior Member davroski's Avatar
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    Default Re: PIC 16F18344 PORTA.5 issue

    Thanks for the quick reply.
    I had set ADCONA.5 = 0 and have now also set WPUA.5 = 1 but to no avail
    I agree with confirming supposed default states in your code as a reference.
    Also the PIC manuals are not infallible. Depending on where you look in the same document you can find the MCLR pin described as read only, or as general I/O
    I also remember a time when a colleague, after some lengthy and 'robust' discussion with Microchip, eventually prompted an admission from them that there was a bug in the chip itself! This was though I admit, a very specific scenario regarding startup timing and not basic I/O.
    I'm a little hampered by the pcb the chip is in so I'll breadboard a test setup with just a DIP chip, a 100n, and an ICSP header. I'll report back here either way for future reference.
    Thanks

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    Junior Member davroski's Avatar
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    Default Re: PIC 16F18344 PORTA.5 issue

    Hmmm.
    Scenario:
    16F18344 with internal 32 MHz clock sitting on its own on a proto board with just a 100n across the 5V.

    Test 1:
    Configure ALL ports for digital input, with pullup resistors enabled.
    Result 1 : ALL ports read high on a logic probe, except RA.5

    Test 2:
    Configure ALL ports for digital output, with all ports set to HIGH.
    Result 1 : ALL ports read high on a logic probe, except RA.5

    [edit] In summary, after more tests, it appears A.5 remains in its startup state of a tri-stated input. Setting a simple program loop to read A.5 and copy the state to an output pin gives a permanent low on the output pin regardless of there being 0V or 5V on A.5.

    I hesitate to suggest the compiler has a glitch when dealing with A.5, but that's a scenario that would fit the evidence so far.

    Does anyone have a quick way of cross checking these simple tests?

    By the way my compiler is IDE Ver 2.0.3.3, and I'm programming the chip via ICSP using a PICkit4 and MPLAB X IPE v5.25

    Thanks
    Dave
    Last edited by davroski; 9th October 2019 at 14:17.

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    Senior Member tumbleweed's Avatar
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    Default Re: PIC 16F18344 PORTA.5 issue

    To the best of my knowledge there's not much that can stop a port pin that's configured for output mode (TRISx=0) from driving the IO pin except a CONFIG setting or the ODCONx open-drain register. The other registers like ANSELx, WPUx, etc won't do it.

    RA5 is also the SOSC/OSC1 pin... perhaps that's something to look at?

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    Default Re: PIC 16F18344 PORTA.5 issue

    SORTED !
    Many thanks for the suggestions, particularly tumbleweed for pointing me towards the OSC settings.

    I experimented with Config1 and found anything other than FEXTOSC_OFF doesn't let A.5 work.

    I still can't see from the datasheet why this is so, but the PIC datasheets are at times really hard work and quite obtuse.

    Thanks again

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