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Thread: PIC18F1330 PLL problem29 days old

  1. #1
    Prolific Poster rcurl's Avatar
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    Default PIC18F1330 PLL problem

    I'm just starting out on a new project that uses a PIC18F1330. I haven't used this specific chip before, so I began by trying to blink an LED just to make sure I've got things working right. My LED is blinking at 1/4 the speed it should, so it appears that the PLL must not be working.
    Could I get someone to take a look at my code to see what i've missed?
    Code:
    Device = 18F1330
    
    Config_Start
      OSC = INTIO2	;Internal oscillator, port function on RA6 and RA7
      FCMEN = OFF	;Fail-Safe Clock Monitor disabled
      IESO = OFF	;Oscillator Switchover mode disabled
      PWRT = On	;PWRT enabled
      BOR = BOHW	;Brown-out Reset enabled in hardware only (SBOREN is disabled)
      BORV = 3	;Minimum setting
      WDT = OFF	;WDT disabled (control is placed on the SWDTEN bit)
      WDTPS = 32768	;1:32768
      PWMPIN = OFF	;PWM outputs disabled upon Reset
      LPOL = High	;PWM0, PWM2 and PWM4 are active-high (default)
      HPOL = High	;PWM1, PWM3 and PWM5 are active-high (default)
      FLTAMX = RA5	;FLTA input is muxed onto RA5
      T1OSCMX = Low	;T1OSO/T1CKI pin resides on RB2
      MCLRE = OFF	;RA5 input pin enabled, MCLR pin disabled
      STVREN = On	;Reset on stack overflow/underflow enabled
      BBSIZ = BB256	;256 Words (512 Bytes) Boot Block size
      XINST = OFF	;Instruction set extension and Indexed Addressing mode disabled
      Debug = OFF	;Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
      Cp0 = OFF	;Block 0 is not code-protected
      CP1 = OFF	;Block 1 is not code-protected
      CPB = OFF	;Boot Block is not code-protected
      CPD = OFF	;Data EEPROM is not code-protected
      WRT0 = OFF	;Block 0 is not write-protected
      WRT1 = OFF	;Block 1 is not write-protected
      WRTC = OFF	;Configuration registers are not write-protected
      WRTB = OFF	;Boot Block is not write-protected
      WRTD = OFF	;Data EEPROM is not write-protected
      EBTR0 = OFF	;Block 0 is not protected from table reads executed in other blocks
      EBTR1 = OFF	;Block 1 is not protected from table reads executed in other blocks
      EBTRB = OFF	;Boot Block is not protected from table reads executed in other blocks
    Config_End
    
    ;**** End of Fuse Configurator Settings ****
    ;-------------------------------------------------------------------------------
    Xtal = 32
    OSCCON =  %01110010   'Internal oscillator 8 Mhz
    OSCTUNE = %01000000   'PLL enabled
    
    '* Set port directions *
    TRISA = %11000000 'A0 is current sense, A1 is light sense, all others outputs
    TRISB = %00000000 'All outputs 
    LATA = 0
    LATB = 0
    
    mainloop:
      Toggle LATB.1
      DelayMS 500
      GoTo mainloop
    It's got to be something simple, but I can't see it.

    Thanks!

    -Rick
    Last edited by rcurl; 21st October 2018 at 12:51.

  2. #2
    Prolific Poster charliecoultas's Avatar
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    Default Re: PIC18F1330 PLL problem

    I don't know where I've seen this Rick, but put a couple of nop's between the OSCCON and OSCTUNE instructions.

    Charlie

  3. #3
    Prolific Poster rcurl's Avatar
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    Default Re: PIC18F1330 PLL problem

    Thanks, Charlie. Unfortunately that didn't do it.

    I haven't needed to write any code in several months, so it's likely I'm making a bonehead mistake somewhere. I've used the PLL many times on other projects and it always seemed to work OK.
    BTW- I should have mentioned it in my first post, but I'm running the internal oscillator at 8Mhz and the PLL should give me a 32Mhz system clock.

    -Rick

  4. #4
    Prolific Poster towlerg's Avatar
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    Default Re: PIC18F1330 PLL problem

    I had a look at the datasheet and worked thro the torrurous pros in section 3.6.4 (PLL IN INTOSC MODES) you seem to be doing everything correctly. I assume that as you're running at 8 Mhz the PLL is not enabled.

    The only suggestion I have (which I'm sure is irrelevant) is to test the IOFS bit before you enable the PLL.

    Edit. Grasping at straws, confirm that FOSC3:FOSC0 is set to 0111
    Last edited by towlerg; 21st October 2018 at 16:21.
    George

  5. #5
    Prolific Poster rcurl's Avatar
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    Default Re: PIC18F1330 PLL problem

    Thanks, George. Testing the IOFS bit didn't help, and I'm not sure how to check FOSC3:FOSC0. The oscillator type is being set by Fuse Configurator.

    -Rick

  6. #6
    Prolific Poster towlerg's Avatar
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    Default Re: PIC18F1330 PLL problem

    As I said, grasping at straws, you can check the actual value of the fuses in the programmer or by hand in the hex file.
    George

  7. #7
    Senior Member Stephen Moss's Avatar
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    Default Re: PIC18F1330 PLL problem

    All looks OK to me, however I noticed some of your settings mix upper and lower case i.e. High & On instead of the all uppercase HIGH & ON that are normally used. I wonder if that is upsetting the compiler in some way, try using all upper case or using the Fuse Configurators format 2 assembler equivalent to eliminate any possible text matching issues.

    Although it should not effect the issue are you sure your TRISA settings are correct as bits 6 & 7 appear to have been set as inputs but the comments suggest the inputs are on A0 & A1.

  8. #8
    Member tumbleweed's Avatar
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    Default Re: PIC18F1330 PLL problem

    Try setting the lower two bits of OSCCON[1:0] (System Clock Select SCS1:SCS0) to 00.
    That will enable the Primary Osc (the one set by the config bits).

    It's not very intuitive, but on many chips you need to set that mode to get the PLL through the clock mux.

  9. #9
    Prolific Poster towlerg's Avatar
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    Default Re: PIC18F1330 PLL problem

    Tumbleweed's remarks made me look at a couple of devices with PLL that I know how to "get going". On the 18F26K22 athought one as OSCCON and the other has OSCCON1 the terminology of the bottom two bits is similar ie SCS1:SCS0. On 18F26K22 I set those two bits to 0 (as Tumbleweed suggests), I can't have read the text or I would have done the same as you or maybe I stole it from somebody!

    I note that on the 18F26K22 datasheet is adds this note to the description of SCS - 00 = Primary clock (determined by FOSC<3:0> in CONFIG1H).
    Last edited by towlerg; 22nd October 2018 at 16:58.
    George

  10. #10
    Member tumbleweed's Avatar
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    Default Re: PIC18F1330 PLL problem

    Quoting my own post...
    That will enable the Primary Osc (the one set by the config bits)
    That comment is wrong.. it enables the primary CLOCK, not the primary OSC.

    That's always confuses most (including me), since they use "Primary" to describe two different settings.

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