With 100 MIPS performance, the core delivers almost double the performance of previous single-core dsPIC® DSCs. It has been designed specifically for controlling multiple sensorless, brushless motors running field-oriented control algorithms and power factor correction.

dsPIC33CK description
dsPIC33CK datasheet

New PIC's are usually supported by PDS sometime after the final product is out due to changes Microchip may make.