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Thread: New dual core dsPIC33CH PIC117 days old

  1. #1
    Prolific Poster normnet's Avatar
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    Default New dual core dsPIC33CH PIC

    The Master core and Slave core can operate
    independently, and can be programmed and debugged
    separately during the application development. Both
    processor (Master and Slave) subsystems have their
    own interrupt controllers, clock generators, ICD, port
    logic, I/O MUXes and PPS. The device is equivalent to
    having two complete dsPIC® DSCs on a single die.

    dsPIC33CH description
    dsPIC33CH datasheet

    New PIC's are usually supported by PDS sometime after the final product is out due to changes Microchip may make.
    Development boards available.

    Norm

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    Prolific Poster normnet's Avatar
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    Default Re: New dual core dsPIC33CH PIC

    What would the max Xtal setting be for this device at 90 and 100 MIPS?
    Last edited by normnet; 26th June 2018 at 02:09.

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    Member basparky's Avatar
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    Default Re: New dual core dsPIC33CH PIC

    Wow. That looks like a new challenge!
    Hope we (proton users) can play with it shortly!

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    Fanatical Contributor fanie's Avatar
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    Default Re: New dual core dsPIC33CH PIC

    Quote Originally Posted by basparky View Post
    Wow. That looks like a new challenge!
    Hope we (proton users) can play with it shortly!
    My worry is the cost of all the motors for so many PWM's...
    I bet the code for it will have a left and a right half of the page. Well, to keep the master and slave synchronized.
    Fanie

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    Fanatical Contributor Les's Avatar
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    Default Re: New dual core dsPIC33CH PIC

    I'm looking into it now, but it is a very querky design.

    It has, what they call, PRAM, and the code for processor 2 sits in processor 1's code memory, then is loaded into PRAM for the second processor to use.
    For more example programs for Proton and Proton24 or updates, please visit: Proton WIKI or Proton Files

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    Prolific Poster normnet's Avatar
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    Default Re: New dual core dsPIC33CH PIC

    Quote Originally Posted by Les View Post
    I'm looking into it now, but it is a very querky design.

    It has, what they call, PRAM, and the code for processor 2 sits in processor 1's code memory, then is loaded into PRAM for the second processor to use.
    Thanks Les. Looking forward to trying out what is probably the fastest new chip in PDS!

    Norm

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    Prolific Poster normnet's Avatar
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    Default Re: New dual core dsPIC33CH PIC

    Page 436 of the dsPIC33CH data sheet gives example code using master and slave utilizing PLL with 8 MHz internal FRC resulting in 200 and 240 MHz or 50 and 60 MIPS. Interestingly the specs list MIPS at 90 and 100 so is this device capable of more than 240 MHz?

    I suspect breadboarding may give way to prototype boards for development due to the speed exceeding the capabilities of breadboarding technique. Start slow on a breadboard and work up.

    Norm

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    Fanatical Contributor Les's Avatar
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    Default Re: New dual core dsPIC33CH PIC

    With PIC24 and dsPIC33 devices, the instruction cycle is 2:1, whereas 8-bit devices have a 4:1 ration.

    So whatever oscillator speed a 16-bit device is capable of running at, divide that by 2 for its MIPS
    For more example programs for Proton and Proton24 or updates, please visit: Proton WIKI or Proton Files

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    Prolific Poster normnet's Avatar
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    Default Re: New dual core dsPIC33CH PIC

    Quote Originally Posted by Les View Post
    With PIC24 and dsPIC33 devices, the instruction cycle is 2:1, whereas 8-bit devices have a 4:1 ration.

    So whatever oscillator speed a 16-bit device is capable of running at, divide that by 2 for its MIPS
    Page 46 of the sdPIC33CH datasheet suggests the MHz 240 is divided by 4 for its MIPS of 60. Missprint?

    Note: FPLLO = FPLLI * M/(N1 * N2 * N3); FPLLI = 8; M = 150; N1 = 1; N2 = 5; N3 = 1;
    so FPLLO = 8 * 150/(1 * 5 * 1) = 240 MHz or 60 MIPS.

    Norm

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    Fanatical Contributor Les's Avatar
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    Default Re: New dual core dsPIC33CH PIC

    See page 439 of the datasheet:

    Each core’s system clock source is divided by two to produce the internal instruction cycle clock.

    The instruction cycle is a division of 2.

    Also, page 1 of the datasheet:

    Operating Conditions
    • 3V to 3.6V, -40°C to +125°C:
    - Master Core: DC to 90 MIPS
    - Slave Core: DC to 100 MIPS







    For more example programs for Proton and Proton24 or updates, please visit: Proton WIKI or Proton Files

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