New dual core dsPIC33CH PIC


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Thread: New dual core dsPIC33CH PIC650 days old

  1. #1
    Prolific Poster normnet's Avatar
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    Default New dual core dsPIC33CH PIC

    The Master core and Slave core can operate
    independently, and can be programmed and debugged
    separately during the application development. Both
    processor (Master and Slave) subsystems have their
    own interrupt controllers, clock generators, ICD, port
    logic, I/O MUXes and PPS. The device is equivalent to
    having two complete dsPIC® DSCs on a single die.

    dsPIC33CH description
    dsPIC33CH datasheet

    New PIC's are usually supported by PDS sometime after the final product is out due to changes Microchip may make.
    Development boards available.

    Norm

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    Prolific Poster normnet's Avatar
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    Default Re: New dual core dsPIC33CH PIC

    What would the max Xtal setting be for this device at 90 and 100 MIPS?
    Last edited by normnet; 26th June 2018 at 02:09.

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    Default Re: New dual core dsPIC33CH PIC

    Wow. That looks like a new challenge!
    Hope we (proton users) can play with it shortly!

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    Fanatical Contributor fanie's Avatar
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    Default Re: New dual core dsPIC33CH PIC

    Quote Originally Posted by basparky View Post
    Wow. That looks like a new challenge!
    Hope we (proton users) can play with it shortly!
    My worry is the cost of all the motors for so many PWM's...
    I bet the code for it will have a left and a right half of the page. Well, to keep the master and slave synchronized.
    Fanie

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    Fanatical Contributor top204's Avatar
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    Default Re: New dual core dsPIC33CH PIC

    I'm looking into it now, but it is a very querky design.

    It has, what they call, PRAM, and the code for processor 2 sits in processor 1's code memory, then is loaded into PRAM for the second processor to use.

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    Prolific Poster normnet's Avatar
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    Default Re: New dual core dsPIC33CH PIC

    Quote Originally Posted by Les View Post
    I'm looking into it now, but it is a very querky design.

    It has, what they call, PRAM, and the code for processor 2 sits in processor 1's code memory, then is loaded into PRAM for the second processor to use.
    Thanks Les. Looking forward to trying out what is probably the fastest new chip in PDS!

    Norm

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    Prolific Poster normnet's Avatar
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    Default Re: New dual core dsPIC33CH PIC

    Page 436 of the dsPIC33CH data sheet gives example code using master and slave utilizing PLL with 8 MHz internal FRC resulting in 200 and 240 MHz or 50 and 60 MIPS. Interestingly the specs list MIPS at 90 and 100 so is this device capable of more than 240 MHz?

    I suspect breadboarding may give way to prototype boards for development due to the speed exceeding the capabilities of breadboarding technique. Start slow on a breadboard and work up.

    Norm

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    Fanatical Contributor top204's Avatar
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    Default Re: New dual core dsPIC33CH PIC

    With PIC24 and dsPIC33 devices, the instruction cycle is 2:1, whereas 8-bit devices have a 4:1 ration.

    So whatever oscillator speed a 16-bit device is capable of running at, divide that by 2 for its MIPS

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    Prolific Poster normnet's Avatar
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    Default Re: New dual core dsPIC33CH PIC

    Quote Originally Posted by Les View Post
    With PIC24 and dsPIC33 devices, the instruction cycle is 2:1, whereas 8-bit devices have a 4:1 ration.

    So whatever oscillator speed a 16-bit device is capable of running at, divide that by 2 for its MIPS
    Page 46 of the sdPIC33CH datasheet suggests the MHz 240 is divided by 4 for its MIPS of 60. Missprint?

    Note: FPLLO = FPLLI * M/(N1 * N2 * N3); FPLLI = 8; M = 150; N1 = 1; N2 = 5; N3 = 1;
    so FPLLO = 8 * 150/(1 * 5 * 1) = 240 MHz or 60 MIPS.

    Norm

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    Default Re: New dual core dsPIC33CH PIC

    See page 439 of the datasheet:

    Each core’s system clock source is divided by two to produce the internal instruction cycle clock.

    The instruction cycle is a division of 2.

    Also, page 1 of the datasheet:

    Operating Conditions
    • 3V to 3.6V, -40°C to +125°C:
    - Master Core: DC to 90 MIPS
    - Slave Core: DC to 100 MIPS








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    Prolific Poster normnet's Avatar
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    Default Re: New dual core dsPIC33CH PIC

    Les

    Progress on support of the new dsPIC33CH...?

    Norm

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    Default Re: New dual core dsPIC33CH PIC

    Update on support for the dual core dsPIC33CH?

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    Default Re: New dual core dsPIC33CH PIC

    I'm busy adding support for the dsPIC33CK and dsPIC33CH devices, but it is a lengthy process. I'm using one of the 28-pin SSOP dsPIC33CK devices on my Positron16 platform board because they are so full of peripherals and can operate so fast. However, the most I can get out of one that is stable is operating at 180MHz with its internal oscillator. It seems that the 200MHz causes problems, and using an external crystal on teh tiny board will remove 2 I/O pins.

    I thought it was just me, but searching on the internet has shown that the 200MHz mark is not really a reality and it causes sticking and oscillator pauses and mis-timings etc.... So the Positron16 platform's libraries will operate at 180MHz (90 MIPS), which is still rather fast at 16-bits, with DSP peripherals built in. :-) An external crystal can still be used on teh Positron16 board, but attached to two of its pins that are brouht out to the world and some fuse and SFR changes.

    For the moment, I am not adding support for the dual modes on the dsPIC33CH devices because they use a very stupid mechanism and it is so prone to faults. Why on earth didn't they just add 2 independent cores with their own Flash with some shared RAM, like other processors do??? Yet again, stupidity based upon Nerds who do not live in the real world.
    Last edited by top204; 20th January 2020 at 11:34.

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  27. #14
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    Default Re: New dual core dsPIC33CH PIC

    Thanks for the update Les! 180 MHz will be a great new device for PDS!

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