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Thread: Voltage limiting to an A/D port1524 days old

  1. #31
    Senior Member Ken_K's Avatar
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    Default Re: Voltage limiting to an A/D port

    Hi Tim
    Lots of jet lag here, this may all be rubbish!

    Idea! Use a series resistor of a few k to prevent any damage to the input.

    In software if a voltage is detected near the maximum use a spare pin the drive the gate of a suitable FET to turn on the bottom resistor of a voltage divider feeding the ADC input.

    If a 2k resistor was in series with the ADC input and a 2k resistor connected from the same node to the FET source (drain to gnd) when the fet was 'on' the input to the ADC would have a lowered Z and the input voltage divided by 2.

    When the pic deemed it safe the input range could switch back from low to high.

    I have used a similar technique with good results, FET RDSon should be low compared to the resistor value.

    Ken

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  3. #32
    Fanatical Contributor Tim's Avatar
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    Default Re: Voltage limiting to an A/D port

    Hi Ken

    Actually that is not a bad idea. I do know when I will get the high voltage and can sample at 1000hz so it will cover the time when not expecting it.

    Tim
    Tim

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    Default Re: Voltage limiting to an A/D port

    Tim

    I found the attached in "Op Amp Applications Handbook - Walt Jung"
    Attached Thumbnails Attached Thumbnails Image1.jpg‎  
    Last edited by towlerg; 6th February 2016 at 23:57.
    George.

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